After swapping the blue and red lanes into the right order - to which I will say, in my defense, I consistently thought the blue+sync lane was lane 2 - I had a clean RGB565 QVGA 60 Hz static image on my monitor. This worked some kinks out of the software, and bringup of the freshly-soldered board was smooth. #Simple tv 0 4 7 r4 download software#This confirmed that the principle was sound, and that my TV and monitor would have no trouble with the output of the matching software encoder on RP2040, provided the chip could physically shove bits out of the pins fast enough.īecause this is a home project, I didn't touch the HDL sim, and stuck to ARM debug, UART and logic analyser for my debugging. I also tried out my slightly harebrained TMDS encoding scheme, which matches the letter but not the spirit of the DVI specification, on an FPGA board with some DVI gateware I wrote for a previous weekend project. I could then dump the TMDS stream with a logic analyser, and examine and parse it on my machine #Simple tv 0 4 7 r4 download serial#
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